As means for generating a stable voltage lower than an input voltage, non-insulated step-down chopper circuits have been widely used. However, such a circuit continues its switching operation even in a light load state such as a standby state, and therefore the lighter the load, the greater the power conversion efficiency decreases.
To solve this problem, a method has been proposed in which an error signal generated by comparing an output voltage and a reference voltage is compared with a predetermined threshold to detect a light load and, once a light load state is reached, the ON and OFF of a switching transistor are controlled according to the pulsation of the error signal to repeat intermittent operations.
In this control method, the lighter the load, the lower the frequency of the switching operation becomes. This enables reduction in the switching loss, and also reduction in the gate drive current of the switching transistor as well. Thus, the efficiency can be improved (U.S. Pat. No. 5,481,178). FIG. 1 illustrates a DC/DC converter described in U.S. Pat. No. 5,481,178.
The DC/DC converter illustrated in FIG. 1 includes an oscillator 1, an SR flip-flop 2, an AND circuit 3, a high-side driver 4, a drive regulator (REG) circuit 5, a backflow preventing diode 6, a bootstrap capacitor 7, a high-side MOSFET 8, an inductor 9, an output capacitor 10, an output load 11, a feedback resistance 12, a feedback resistance 13, an error amplifier 14, a phase compensation resistance 15, a phase compensation capacitor 16, a PWM comparator 17, an inverter 18, a NOR circuit 19, a low-side driver 20, a low-side MOSFET 21, a zero crossing detection circuit 22, a light load detection comparator 23, a constant current source Ibias1, and a constant current source Ibias2.
Next, operations in a steady load state (Iout>Iskip_in) range will first be described with reference to a timing chart illustrated in FIG. 2.
An output voltage Vout is divided by the feedback resistance 12 and the feedback resistance 13 to generate a feedback voltage FB. The feedback voltage FB is inputted to the inverting input terminal of the error amplifier 14, whereas a reference voltage Vref is input to the non-inverting input terminal of the error amplifier 14. The error amplifier 14 generates an amplified error signal COMP from the feedback voltage FB and the reference voltage Vref. The amplified error signal COMP is outputted to the inverting input terminal of the PWM comparator 17 and the inverting input terminal of the light load detection comparator 23. A first light load detection threshold Vsk_Lo is inputted to the non-inverting input terminal of the light load detection comparator 23. When an output load current Iout is sufficiently large, COMP>Vsk_Lo holds, and thus an output signal SKIP of the light load detection comparator 23 is at a low level, and the light load detection comparator 23 outputs a low level signal to the input of the inverter circuit 18. As a result, an intermittent oscillation operation is disabled.
The constant current source Ibias2 is connected to the oscillator 1, and the oscillator 1 generates set pulses based on the constant current source Ibias2 and outputs the set pulses to a set terminal S of a PWM latch 2.
The constant current source Ibias1 is connected to the drive REG circuit 5, and the drive REG circuit 5 supplies a drive voltage to the low-side drive circuit 20 and to the high-side drive circuit 4 through the backflow preventing diode 6.
When the PWM latch 2 shifts to a set state, the high-side driver 4 is driven through the AND circuit 3, so that the high-side MOSFET 8 is turned on. In this step, the voltage of an SW terminal rises to near the voltage of a DC power source Vin, and a current IDH corresponding to the voltage difference between the SW terminal and a Vout terminal flows into the inductor 9. As a result, energy is supplied to the output capacitor 10 and the output load 11.
On the other hand, a high-side current detection signal Vtrip proportional to the drain current IDH of the high-side MOSFET 8 is inputted to the non-inverting input terminal of the PWM comparator 17. The PWM comparator 17 outputs a reset signal RESET to the PWM latch 2 when the high-side current detection signal Vtrip reaches or exceeds the amplified error signal COMP during the ON period of the high-side MOSFET 8. When the PWM latch 2 shifts to a reset state, the high-side driver 4 is turned off through the AND circuit 3, and the low-side driver 20 is turned on through the NOR circuit 19. Thus, the high-side MOSFET 8 is switched from on to off, and the low-side MOSFET 21 is switched from off to on. Accordingly, a regeneration current IDL is supplied to the inductor 9 from the source of the low-side MOSFET 21 through the drain thereof.
In a case of a continuous current operation in which the regeneration of the inductor 9 is not completed within an oscillation cycle determined by the oscillator 1, the PWM latch 2 again shifts to the set state, so that the low-side MOSFET 21 is turned off and the high-side MOSFET 8 is turned on.
By repeating the operations described above, a step-down chopper operation is performed. Next, operations performed when the load state shifts from the steady load state to a light load state and then returns to the steady load state will be described with reference to FIG. 2. As Iout decreases, the amplified error signal COMP decreases. Thus, the peak value of the drain current IDH of the high-side MOSFET 8 is controlled to be small. The light load detection comparator 23 compares the amplified error signal COMP and the first light load detection threshold Vsk_Lo. When the amplified error signal COMP falls below the first threshold Vsk_Lo, the first threshold Vsk_Lo is switched to a second threshold Vsk_Hi, and a light load detection signal SKIP is switched from low to high. As a result, the high-side MOSFET 8 is forcibly turned off through the inverter 18, the AND circuit 3, and the high-side driver 4. Then, when the zero crossing detection circuit 22 detects that the regeneration period of the inductor 9 is completed, and a zero crossing signal ZERO is switched from low to high, the low-side MOSFET 21 is turned off through the NOR circuit 19 and the low-side driver 20.
Thereafter, when the electric charge of the output capacitor 10 is discharged by the output current Tout during the period in which the intermittent oscillation switching operation is stopped, the output voltage Vout slightly decreases and the potential difference between the voltage of an FB terminal and the voltage Vref widens. As a result, the amplified error signal COMP rises.
When the amplified error signal COMP reaches or exceeds the second light load threshold Vsk_Hi, the light load detection comparator 23 switches the light load detection signal SKIP from high to low, so that the light load detection threshold is switched from the second threshold Vsk_Hi to the first threshold Vsk_Lo. In this step, the output of the inverter 18 is switched from low to high, so that the switching operation resumes.
By repeating the series of operations described above, an intermittent oscillation operation is performed, and control is performed such that the smaller the output current Iout, the longer the intermittent oscillation cycle becomes. Thus, the switching loss that occurs at the high-side MOSFET 8 and the low-side MOSFET 21 is reduced. Accordingly, the efficiency in the light load state is improved.
Thereafter, as Iout increases, the length of time required to lower Vout during the intermittent oscillation OFF period shortens according to the increase in Iout, and thereby the intermittent oscillation cycle shortens. Once the amplified error signal COMP rises and never falls below the first light load detection threshold Vsk_Lo, the operation shifts to the steady oscillation operation.
As a proposal to reduce the number of times switching is performed during a light load state, Japanese Patent Application Publication No. 2007-020352 proposes a step-down chopper which detects an output voltage with a hysteresis comparator, turns off a switching element when the detected voltage reaches a first threshold and turns on the switching element when the detected voltage reaches a second threshold smaller than the first threshold, and shifts the second threshold to a higher potential side by a predetermined voltage width during a light load state.
However, in the case of U.S. Pat. No. 5,481,178, there is a first problem as below. Specifically, there is a propagation delay in the PWM comparator 17. Thus, when the current detection signal Vtrip reaches the amplified error signal COMP, the PWM comparator 17 cannot quickly output a reset signal to the PWM latch 2 and turn off the high-side MOSFET 8. For this reason, the amplified error signal COMP is controlled in advance to a voltage lower than a target level. The propagation delay is constant. Thus, as illustrated in FIG. 3A, in a condition where Vout is relatively high (small voltage difference between Vin and Vout), each ON period of the high-side MOSFET 8 (corresponding to each ON period of Vtrip in FIG. 3A) is sufficiently long as compared to a propagation delay ΔT, and therefore the propagation delay ΔT is not particularly problematic.
However, in a condition where Vout is set to be relatively low (large difference between Vin and Vout), each ON period of the high-side MOSFET 8 (corresponding to each ON period of Vtrip in FIG. 3B) is so short that the influence of the propagation delay cannot be ignored, and the amplified error signal COMP has to be controlled to a voltage significantly smaller than the target level. The light load detection comparator 23 compares this amplified error signal COMP and the first light load detection threshold Vsk_Lo for light load detection. In this connection, as illustrated in FIG. 9, the current level for light load determination (light load detection threshold) is larger for a condition with lower Vout. This leads to a problem in that an intermittent oscillation operation is performed even in a heavy load range where a steady oscillation operation should be performed.
Moreover, there is a second problem as below. Specifically, when the high-side MOSFET 8 is turned on during an intermittent oscillation period, Vout rises, and the voltage difference between the voltage of the FB terminal and the reference voltage Vref increases. Thus, the amplified error signal COMP drops, and the light load detection signal SKIP again is switched from low to high, so that the operations of the high-side MOSFET 8 and the low-side MOSFET 21 are stopped. In the real situation, however, there is a response delay in the amplified error signal COMP, and the amplified error signal COMP cannot quickly drop below the first light load detection threshold (Vsk_Lo). As a consequence, multiple switching operations are performed within one intermittent oscillation cycle as illustrated in FIG. 2. Thus, the ripple voltage superimposed on Vout is increased, and the intermittent oscillation OFF period becomes unnecessarily long. As a result, the intermittent oscillation frequency may become lower than the human hearing range (20 kHz or below). In a case of using a ceramic capacitor as the output capacitor 10, such frequency leads to a problem in that acoustic noises are generated due to its piezoelectric effect.
Moreover, there is a third problem in that there is no current difference between the load current at which the intermittent oscillation operation is started and the load current at which the intermittent oscillation operation is ended, and therefore the operation becomes unstable in a near-threshold load range. According to Japanese Patent Application Publication No. 2007-020352, the second problem may be reduced, but the first and third problems are not yet to be solved.
An object of the present invention is to provide a DC/DC converter capable of disabling an intermittent oscillation operation in a heavy load range without increasing a light load detection threshold even in a condition where an output voltage is low.